Efficient Application Mapping on CGRAs based on Backward Simultaneous Scheduling/Binding and Dynamic Graph Transformations

Thomas Peyret (1) , Gwenolé Corre (1) , Mathieu Thevenin (1) , Kevin Martin (2) , Philippe Coussy (2)

1 LCAE (CEA, LIST) - Laboratoire Capteurs et Architectures Electroniques (CEA, LIST)
2 Lab-STICC_UBS_CACS_MOCS

Mapping an application on a coarse grained reconfigurable architecture (CGRA) is a complex task which is still often completely or partially realized manually. This paper presents an automated synthesis flow based on simultaneous scheduling and binding steps. The proposed method uses a backward traversal of the formal model obtained after compilation and dynamically transforms it when needed. Our approach is compared with state of the art techniques and its interest is shown through the mapping of several applications from digital signal and image processing domain.

Mots clés: Routing; Space exploration; Dynamic scheduling; data flow graph; backward simultaneous scheduling-binding; dynamic graph transformations; application mapping; coarse grained reconfigurable architecture; automated synthesis flow; backward traversal; formal model; compilation; digital signal domain; image processing domain; CGRA; Coarse-Grained Reconfigurable Architecture (CGRA); Mapping; Scheduling; Binding; Registers; Reconfigurable architectures; Electronic architecture; instrumentation

Domaines: Ingénierie assistée par ordinateur; Traitement du signal et de l'image [eess.SP]; Arithmétique des ordinateurs; Electronique

Thomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin Martin, Philippe Coussy. Efficient Application Mapping on CGRAs based on Backward Simultaneous Scheduling/Binding and Dynamic Graph Transformations. IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Jun 2014, Zurich, Switzerland. pp.6868652, ⟨10.1109/ASAP.2014.6868652⟩. ⟨hal-01009486⟩