A 2GHz CMOS DCO with optimized architecture for high speed clocking

Eldar Zianbetov (1) , Mohammad Javidan (1) , François Anceau (1) , Dimitri Galayko (1) , Eric Colinet (2) , Jérôme Juillard (3)

1 CIAN - Circuits Intégrés Numériques et Analogiques
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 E3S - Supélec Sciences des Systèmes

Domains: Engineering Sciences [physics]; Electronics; Engineering Sciences [physics]; Signal and Image processing; Computer Science [cs]; Signal and Image Processing

Eldar Zianbetov, Mohammad Javidan, François Anceau, Dimitri Galayko, Eric Colinet, et al.. A 2GHz CMOS DCO with optimized architecture for high speed clocking. International Symposium on Circuits and Systems (ISCAS'11), May 2011, Rio de Janeiro, Brazil. pp.2845-2848. ⟨hal-00631096⟩