Transconductance / Drain Current Based Sensitivity Analysis for Analog CMOS Integrated Circuits

Abstract : Recent studies have shown that transistor variability and ageing phenomena are responsible for variation of transconductance (gm) and drain current (ID) in MOSFETs. It is therefore important to perform sensitivity analysis at the earliest design stage in order to minimize effects of ageing. It is however not trivial to perform sensitivity analysis analytically because the 1-V characteristics of modern transistors can not modeled without using complicated expressions. In this paper, We propose a technique that utilizes the transconductance-to-drain current ratio (gm/ID) of a transistor to captures the sensitivity of a circuit. This technique is applicable to transistors biased in all regions of operations. To explore the effectiveness of the proposed technique in practical circuit design, the sensitivity of a common source amplifier is analyzed. The proposed technique has an accuracy of ± 15 % between 4 <; gm/ID<; 28.
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Communication dans un congrès
IEEE International New Circuits and Systems Conference (NEWCAS), Jun 2013, Paris, France. 〈10.1109/NEWCAS.2013.6573605〉
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https://hal-centralesupelec.archives-ouvertes.fr/hal-01222134
Contributeur : Pietro Maris Ferreira <>
Soumis le : jeudi 29 octobre 2015 - 11:49:36
Dernière modification le : jeudi 11 janvier 2018 - 06:19:15

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Jack Ou, Pietro Maris Ferreira. Transconductance / Drain Current Based Sensitivity Analysis for Analog CMOS Integrated Circuits. IEEE International New Circuits and Systems Conference (NEWCAS), Jun 2013, Paris, France. 〈10.1109/NEWCAS.2013.6573605〉. 〈hal-01222134〉

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