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A New Synthesis Methodology for Reliable RF front-end Design

Abstract : A low power and low cost WLAN/WiMAX RF front- end requires more advanced CMOS technologies whose transistor parameters degradation is becoming worse. Few published works has presented the reliability results for RF circuits. In order to fill this gap, we develop a new synthesis methodology for reliable RF front-end design using the design example of a reliable BLIXER. The first steps of our synthesis methodology is a transistor ageing simulation. Then, we calculate an estimation of the circuit performance and ageing using the circuit design equations and the total derivatives. Thus, we can find the required bias and sizing improving the circuit reliability. The simulation results of the typical circuit are coherent with the WLAN/WiMAX RF front-end specifications. Despite the integrated process variability and mismatch, we observe that 96.4 % of the simulation runs have Gain >; 10.0 dB, and 92.1% of the simulation runs have NFmax <; 5.0 dB. Moreover, the BLIXER ageing degradation is negligible according to the fitted Poisson distribution of the power consumption for 99.9% of confidence. Going further, we can say that the synthesis methodology proposed and developed for a RF front-end design can be exploited in different AMS/RF circuits and also generalized for a single bottom- up reliable-system design approach.
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https://hal-centralesupelec.archives-ouvertes.fr/hal-01222152
Contributor : Pietro Maris Ferreira <>
Submitted on : Thursday, October 29, 2015 - 12:09:57 PM
Last modification on : Friday, July 31, 2020 - 10:44:08 AM

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Pietro Maris Ferreira, Hervé Petit, Jean-François Naviner. A New Synthesis Methodology for Reliable RF front-end Design. IEEE International Symposium on Circuits and Systems (ISCAS), May 2011, Rio de Janeiro, RJ, Brazil. ⟨10.1109/ISCAS.2011.5938204⟩. ⟨hal-01222152⟩

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