A new two-step Σ∆ architecture column-parallel ADC for CMOS image sensor

Abstract : The demand for high resolution CMOS image sensors (CIS) is rising. Analog-to-digital converters (ADC) represent one of the major bottleneck of CIS. One of the candidates to overcome the existing limits is the column-parallel ADC. Column-parallel extended counting ADCs (EC-ADC) are able to reach high resolution thanks to their two-step conversion. However the EC-ADC area increases due to the two-step design. A solution is to use the same hardware twice to perform both steps. This paper proposes a 14-b, 100 kHz Nyquist frequency, two-step incremental Σ∆ (IΣ∆) analog-to-digital converter suitable for column-parallel CIS. Several architectures with different modulator order are compared to determine the most promising one. The proposed architecture, compared to a one-step second order modulator, reduces the total oversampling ratio (OSR) from 150 to 60 to reach a resolution of 14-b. The operational transconductance amplifiers (OTA) is the most critical part in our ADCs. Its required DC-gain is around 80 dB for a 120 MHz gain-bandwidth product (GBW). The ideal DNL and INL of our two-step IΣ∆ ADC are respectively +0.55/-0.6 LSB and +0.5/-0.5 LSB. This work achieves a SNDR of 89 dB when a full scale sinusoid of 100 kHz is applied. Index Terms—ADC, incremental, sigma-delta (Σ∆), two-step, CMOS Image Sensor, column-parallel ADC, second-order Σ∆
Type de document :
Communication dans un congrès
2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI) , Aug 2016, Belo Horizonte, Brazil. 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI) 〈10.1109/SBCCI.2016.7724065〉
Liste complète des métadonnées

Littérature citée [19 références]  Voir  Masquer  Télécharger

https://hal-centralesupelec.archives-ouvertes.fr/hal-01357892
Contributeur : Alexandra Siebert <>
Soumis le : jeudi 1 septembre 2016 - 10:29:07
Dernière modification le : jeudi 5 avril 2018 - 12:30:24
Document(s) archivé(s) le : vendredi 2 décembre 2016 - 16:08:21

Fichier

sbcci_v3_final_readystate1.pdf
Fichiers produits par l'(les) auteur(s)

Identifiants

Citation

Pierre Bisiaux, Caroline Lelandais-Perrault, Anthony Kolar, Philippe Benabes, Filipe Vinci dos Santos. A new two-step Σ∆ architecture column-parallel ADC for CMOS image sensor. 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI) , Aug 2016, Belo Horizonte, Brazil. 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI) 〈10.1109/SBCCI.2016.7724065〉. 〈hal-01357892〉

Partager

Métriques

Consultations de la notice

241

Téléchargements de fichiers

424