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An ultra-thin SiO2 ALD layer for void-free bonding of III–V material on silicon

A. Talneau 1 K. Pantzas 1 A. Durnez 1 G. Patriarche 1 D. Alamarguy 2 E. Le Bourhis 3
1 LPN - Laboratoire de photonique et de nanostructures
2 GeePs - Laboratoire Génie électrique et électronique de Paris
3 PPRIME - Institut Pprime
Keywords : ALD process Dangling bonds Hybrid interface Hybrid bonding XPS X-ray Photoélectron Spectroscopy III-V on Silicon SiO2 ALD layer
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Journal articles
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https://hal-centralesupelec.archives-ouvertes.fr/hal-01449032
Contributor : David Alamarguy <>
Submitted on : Monday, January 30, 2017 - 1:48:03 AM
Last modification on : Tuesday, July 20, 2021 - 3:04:17 AM

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CENTRALESUPELEC | CNRS | UPMC | GEEPS | UNIV-POITIERS | PHEMADIC | SORBONNE-UNIVERSITE | SU-SCIENCES | PPRIME | GS-ENGINEERING

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A. Talneau, K. Pantzas, A. Durnez, G. Patriarche, D. Alamarguy, et al.. An ultra-thin SiO2 ALD layer for void-free bonding of III–V material on silicon. Microelectronic Engineering, Elsevier, 2016, 162, pp.40 - 44. ⟨10.1016/j.mee.2016.05.001⟩. ⟨hal-01449032⟩

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