Impacts of Crest Factor Reduction and Digital Predistortion on Linearity and Power Efficiency of Power Amplifiers - Archive ouverte HAL Access content directly
Journal Articles IEEE Transactions on Circuits and Systems II: Express Briefs Year : 2018

Impacts of Crest Factor Reduction and Digital Predistortion on Linearity and Power Efficiency of Power Amplifiers

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Abstract

The linearity and power efficiency are two main factors of power amplifiers (PA), which can hardly be improved together. Digital predistortion (DPD) compensates for nonlinearity and memory effects of PAs in high efficiency zone. However, for advanced communication standards the high peak-to-average power ratio of the modulated signal constrains the PA operating point and thus limits the power efficiency. Crest factor reduction (CFR) techniques are applied to address this problem though they degrade the PA linearity relatively. In this paper, we compare different CFR approaches with respect to their performances in terms of linearity, PA power efficiency, and computational complexity. Classical hard clipping, clip-and-filter as well as joint CFR/DPD methods are considered. To complete the comparison, we propose a modeled CFR identified using indirect learning architecture combined with DPD. The simulation results validate its effectiveness on the trade-off among linearity, PA power efficiency and CFR computational complexity.
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Dates and versions

hal-01846123 , version 1 (20-07-2018)

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Siqi Wang, Morgan Roger, Caroline Lelandais-Perrault. Impacts of Crest Factor Reduction and Digital Predistortion on Linearity and Power Efficiency of Power Amplifiers. IEEE Transactions on Circuits and Systems II: Express Briefs, 2018, 66 (3), pp.407-411. ⟨10.1109/TCSII.2018.2855084⟩. ⟨hal-01846123⟩
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