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Temperature-Aware gm/ID-based Methodology for Active Inductor Design

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Abstract

Active inductors have become standard building blocks for many applications by its recon gurability and reduced silicon area. However, the inductance variation over temperature is a main circuits' limitation in harsh environments. This paper presents a novel temperature analysis of a general architecture of active inductors, obtaining an optimal conductance value to minimize inductance variation over temperature. Based on the m /I D and sensitivity analysis, temperature variation result highlights that, even if its counter intuitive to bias transistors in weak inversion, a low inductance variation of 139 ppm/ °C.
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Dates and versions

hal-02268794 , version 1 (23-09-2019)

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  • HAL Id : hal-02268794 , version 1

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João R. Raposo de O. Martins, Emilie Avignon-Meseldzija, Pietro Maris Ferreira. Temperature-Aware gm/ID-based Methodology for Active Inductor Design. Workshop on Circuits and System Design, Aug 2019, São Paulo, Brazil. ⟨hal-02268794⟩
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