Skip to Main content Skip to Navigation
Conference papers

An OpenCL pipeline implementation on Intel FPGA for 3D backprojection

Abstract : 3D back-projector computation is a time-consuming task, and hardware accelerators are used in order to speedup this algorithm. We propose a pipeline implementation of the 3D back-projection algorithm on a high-end FPGA using Intel FPGA SDK for OpenCL while presenting some optimization metrics for task par-allelism. Compared to a non-optimized version on Arria 10, we achieved a speedup of 23 regarding execution time, by applying these techniques properly. We then compared these results with a low-end FPGA, CPU and GPU in terms of execution time and energy efficiency. Index Terms-Algorithm architecture co-design, Intel FPGA SDK for OpenCL, hardware acceleration, FPGA, Computed Tomography.
Document type :
Conference papers
Complete list of metadata

https://hal-centralesupelec.archives-ouvertes.fr/hal-02500994
Contributor : Daouda Diakite <>
Submitted on : Monday, March 8, 2021 - 3:45:04 PM
Last modification on : Thursday, April 1, 2021 - 3:35:42 AM

File

diakite et al.pdf
Files produced by the author(s)

Identifiers

  • HAL Id : hal-02500994, version 2

Citation

Daouda Diakite, Maxime Martelli, Nicolas Gac. An OpenCL pipeline implementation on Intel FPGA for 3D backprojection. 6th International Conference on Image Formation in X-Ray Computed Tomography, Aug 2020, Regensburg, Germany. ⟨hal-02500994v2⟩

Share

Metrics

Record views

26

Files downloads

31