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An OpenCL pipeline implementation on Intel FPGA for 3D backprojection

Abstract : 3D back-projector computation is a time-consuming task, and hardware accelerators are used in order to speedup this algorithm. We propose a pipeline implementation of the 3D back-projection algorithm on a high-end FPGA using Intel FPGA SDK for OpenCL while presenting some optimization metrics for task par-allelism. Compared to a non-optimized version on Arria 10, we achieved a speedup of 23 regarding execution time, by applying these techniques properly. We then compared these results with a low-end FPGA, CPU and GPU in terms of execution time and energy efficiency. Index Terms-Algorithm architecture co-design, Intel FPGA SDK for OpenCL, hardware acceleration, FPGA, Computed Tomography.
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https://hal-centralesupelec.archives-ouvertes.fr/hal-02500994
Contributor : Daouda Diakite <>
Submitted on : Friday, March 6, 2020 - 2:45:22 PM
Last modification on : Saturday, October 3, 2020 - 4:16:02 AM
Long-term archiving on: : Sunday, June 7, 2020 - 3:12:23 PM

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  • HAL Id : hal-02500994, version 1

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Daouda Diakite, Maxime Martelli, Nicolas Gac. An OpenCL pipeline implementation on Intel FPGA for 3D backprojection. 6th International Conference on Image Formation in X-Ray Computed Tomography, Aug 2020, Regensburg, Germany. ⟨hal-02500994⟩

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