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An OpenCL pipeline implementation on Intel FPGA for 3D backprojection

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Daouda Diakite
Nicolas Gac

Abstract

3D back-projector computation is a time-consuming task, and hardware accelerators are used in order to speedup this algorithm. We propose a pipeline implementation of the 3D back-projection algorithm on a high-end FPGA using Intel FPGA SDK for OpenCL while presenting some optimization metrics for task par-allelism. Compared to a non-optimized version on Arria 10, we achieved a speedup of 23 regarding execution time, by applying these techniques properly. We then compared these results with a low-end FPGA, CPU and GPU in terms of execution time and energy efficiency. Index Terms-Algorithm architecture co-design, Intel FPGA SDK for OpenCL, hardware acceleration, FPGA, Computed Tomography.
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Dates and versions

hal-02500994 , version 1 (06-03-2020)
hal-02500994 , version 2 (08-03-2021)

Identifiers

  • HAL Id : hal-02500994 , version 2

Cite

Daouda Diakite, Maxime Martelli, Nicolas Gac. An OpenCL pipeline implementation on Intel FPGA for 3D backprojection. 6th International Conference on Image Formation in X-Ray Computed Tomography, Aug 2020, Regensburg, Germany. ⟨hal-02500994v2⟩
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