Analog bandwidth mismatch compensation for time-interleaved ADCs using FD-SOI technology

Abstract : This paper introduces an analog bandwidth mismatch compensation technique for Time-Interleaved Analog-to-Digital Converters (TI-ADCs). It takes advantage of a Fully Depleted Silicon On Insulator (FD-SOI) technology to compensate for the bandwidth mismatch errors among channels. Our technique utilizes the body-effect to adjust the on-resistance of the sampling switch, by means of a 6-bit Digital-to-Analog-Converter (DAC). Simulations of a 2-channel TI-ADC running at fs= 4GHz shows the effectiveness of the correction. The spurious-free dynamic range (SFDR) is improved from 44.63 dB to 83.12 dB for a sine-wave just below the Nyquist frequency(fNyquist) of 2 GHz.
Type de document :
Communication dans un congrès
2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017) , May 2017, Baltimore, MD, United States. 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017) 〈http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8014728〉. 〈10.1109/ISCAS.2017.8050246〉
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https://hal-centralesupelec.archives-ouvertes.fr/hal-01659299
Contributeur : Caroline Lelandais-Perrault <>
Soumis le : vendredi 8 décembre 2017 - 11:48:11
Dernière modification le : mardi 12 juin 2018 - 01:19:06

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Alexandre Mas, Eric André, Caroline Lelandais-Perrault, Filipe Vinci dos Santos, Philippe Benabes. Analog bandwidth mismatch compensation for time-interleaved ADCs using FD-SOI technology. 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017) , May 2017, Baltimore, MD, United States. 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017) 〈http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8014728〉. 〈10.1109/ISCAS.2017.8050246〉. 〈hal-01659299〉

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