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A General gm/Id Temperature-Aware Design Methodology Using 180 nm CMOS up to 250 °C

Abstract : The advent of the Internet-of-Things brings new challenges in circuit design. The presence of circuits and sensors in harsh environments brought the need for methodologies that account for them. Since the beginning of the transistors, the temperature is known for having a significant impact on performance, and even though very low temperature sensitivity circuits have been proposed, no general methodology for designing them exists. This paper proposes an extension of the methodology presented in [15], generalizing the gm/ID technique for designing temperature-aware circuits that can be used either on measurement data, analytically, or based on simulation models. This model is validated using measurements up to 250°C of X-FAB XT018 transistors and later with a Voltage-Controlled Oscillator circuit design example.
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Contributor : Pietro Maris Ferreira Connect in order to contact the contributor
Submitted on : Tuesday, June 7, 2022 - 1:08:35 PM
Last modification on : Saturday, June 25, 2022 - 3:34:58 AM
Long-term archiving on: : Thursday, September 8, 2022 - 6:45:02 PM


Martins et al. - A General gmI...
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João R. Raposo de O. Martins, Francisco de Oliveira Alves, Pietro Maris Ferreira. A General gm/Id Temperature-Aware Design Methodology Using 180 nm CMOS up to 250 °C. Journal of Integrated Circuits and Systems, 2022, 17 (1), pp.1 - 9. ⟨10.29292/jics.v17i1.552⟩. ⟨hal-03689553⟩



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